Carrier Board Design Guide


Carrier Board Design Guide

Overview

The Cubic-SoC family of modules are designed to take most of the pain out of developing a new product based on the Altera Cyclone V FPGAs that include ARM processing core[s]. The long list of requirements and costly board design specifications are handled by the module as much as possible. This, along with the board support package, makes it possible to quickly create new products with greatly reduced effort relative to creating a complete system design from scratch.

Fast Facts for Getting Started

FactsCubic-SoC
Required socket connectorMXM Connector, or equivalent
Input voltage Required5V
Memory PeripheralsLPDDR2 SDRAM, QSPI NOR Flash, SD(Micro SD Socket)
On-Module HPS PeripheralsUSB1, UART0, EMAC1
HPS Edge PeripheralsUART1,CAN0,1, I2C0,1, SPIM0,1, and SPIS0,1
HPS Fabric Peripherals(by loan IO)EMAC0,1,USB0, CAN0,1, UART0,1, I2C0,1,2, and SPIM0,1
Total number of FPGA I/Os112
Differential I/Os42 pairs
Clock Differential I/Os2 pairs
Single Ended I/Os24

Table 1 above gives an idea of the peripherals and features available on the Cubic-SoC. Additional details can be found in the list below with the HPS peripherals grouped by the FPGA Bank.

  • Bank7A includes a mix of module peripherals and exposed HPS peripherals (+3.3V)

> UART0 Console Interface (by default in BSP)

> TRACE Peripheral can be directed tor the edge connector

> With the JTAG/TRACE adapter in TRACE Mode, the TRACE pins are used on the module

> SPIM0 / I2C1 / UART0 Flow Control / CAN1 / GPIOs

> CAN0 / GPIOs

> 25MHz HPS-CLK1 and HPS-CLK2 oscillator

  • Bank7C has 4 GPIO to exposed to the edge connector (+3.3V I/O)
  • Bank7B uses the QSPI1 peripheral for NOR flash and RGMII for Ethernet
  • Bank7D uses the USB1 peripheral for USB OTG

 

Cubic-SoC Family Module

The Cubic-SoC family of modules is available in a few configurations. These options provide a range of FPGA fabric and memory sizes to meet a range of applications.

 

Module Dimension

The Cubic-SoC modules measure 70mm x 33mm. A dimensioned drawing of the module is shown in Figure 1. All dimensions shown are in millimeters.

Figure 1

Figure 1

Connectors

The primary interface connector for Cubic-SoC-5CSX is the 230-pin card edge interface which contains 8 classes of signals:

  • Power (PWR).
  • Dedicated Ethernet signals (Ethernet Dedicated).
  • Dedicated USB signals (USB Dedicated)
  • Dedicated JTAG signals (JTAG Dedicated)
  • Multi-function signals mapped to the Cyclone V SoC HPS pins (HPS IO)
  • General purpose I/O pins mapped to the Cyclone V SoC FPGA pins (FPGA IO)
  • Dedicated signals mapped to the Cyclone V SoC HPS (HPS Dedicated)
  • Dedicated 3.125Gbps Transceiver signals mapped to the Cyclone V SoC (Transceiver Dedicated)

Table 7 contains a summary of the Cubic-SoC-5CSX pin-mapping.

The Cubic-SoC-5CSX module mates with a single connector that contains all of the power and I/O for the module. The mating socket is a 230-pin MXM 2.0 type connector which is also used for PCI Express capable notebook graphics cards following the MXM specification. Therefore, this connector type is also known as a MXM connector.

The MXM edge connector is the result of an extensive collaborative design effort with the industry’s leading notebook manufacturers. This collaboration has produced a robust, low-cost edge connector that is capable of handling high-speed serialized signals. The MXM connector accommodates various connector heights for different carrier board applications needs. This specification suggests two connector heights, 7.8mm and 5.5mm.

Table 6 MXM2.0 Connector

ManufacturerPart NumberResulting height
between module and baseboard
Overall height of the connector
FoxconnAS0B326-S78N-7F5.0mm7.8mm
FoxconnAS0B326-S55N-7F2.7mm5.5mm
SpeedtechB33P102-XX1X5.0mm7.5mm
SpeedtechB33P102-XX2X2.7mm5.2mm

Table 7: Edge Connector Pin-Out

Module Pin NumberClassVoltageNet NameFPGA PinDedicated Tx/Rx ChannelHPS BootHPS Pin Mux Select 3HPS Pin Mux Select 2HPS Pin Mux Select 1HPS Pin Mux Select 0
1PWRGND
2PWRGND
3Ethernet Dedicated3.3VMDI_N3
4Ethernet Dedicated3.3VMDI_N2
5Ethernet Dedicated3.3VMDI_P3
6Ethernet Dedicated3.3VMDI_P2
7Ethernet Dedicated3.3VLED1
8Ethernet Dedicated3.3VLED2
9Ethernet Dedicated3.3VMDI_N1
10Ethernet Dedicated3.3VMDI_N0
11Ethernet Dedicated3.3VMDI_P1
12Ethernet Dedicated3.3VMDI_P0
13HPS IO3.3VHPS_SPIM0_SS1A17UART0_RXCAN0_RXSPIM0_SS1HPS_GPIO61
14HPS IO3.3VHPS_SPIM1_SS1H17CLKSEL1UART0_TXCAN0_TXSPIM1_SS1HPS_GPIO62
15HPS IO3.3VHPS_SPIM0_CLKA18SPIM0_CLKI2C1_SDAUART0_CTSHPS_GPIO57
16HPS IO3.3VHPS_SPIM1_CLKC19I2C0_SDAUART1_RXSPIM1_CLKHPS_GPIO63
17HPS IO3.3VHPS_SPIM0_MOSIC17SPIM0_MOSII2C1_SCLUART0_RTSHPS_GPIO58
18HPS IO3.3VHPS_SPIM1_MOSIB16I2C0_SCLUART1_TXSPIM1_MOSIHPS_GPIO64
19HPS IO3.3VHPS_SPIM0_MISOB18SPIM0_MISOCAN1_RXUART1_CTSHPS_GPIO59
20HPS IO3.3VHPS_SPIM1_MISOB19CAN0_RXUART0_RXSPIM1_MISOHPS_GPIO65
21HPS IO3.3VHPS_SPIM0_SS0J17SPIM0_SS0CAN1_TXUART1_RTSHPS_GPIO60
22HPS IO3.3VHPS_SPIM1_SS0C16CLKSEL0CAN0_TXUART0_TXSPIM1_SS0HPS_GPIO66
23PWRGND
24PWRGND
25PWRGND
26PWRGND
27HPS IO3.3VHPS_UART_TXB21TRACE_D1SPIS0_MOSIUART0_TXHPS_GPIO50
28HPS IO3.3VHPS_CAN_TXJ18TRACE_D5SPIS1_MOSICAN1_TXHPS_GPIO54
29HPS IO3.3VHPS_UART_RXA22TRACE_D0SPIS0_CLKUART0_RXHPS_GPIO49
30HPS IO3.3VHPS_CAN_RXA20TRACE_D4SPIS1_CLKCAN1_RXHPS_GPIO53
31HPS IO3.3VHPS_I2C1_SDAA21TRACE_D2SPIS0_MISOI2C1_SDAHPS_GPIO51
32HPS IO3.3VHPS_I2C1_CLKK18TRACE_D3SPIS0_SS0I2C1_SCLHPS_GPIO52
33HPS IO3.3VHPS_I2C0_SDAA19TRACE_D6SPIS1_SS0I2C0_SDAHPS_GPIO55
34HPS IO3.3VHPS_I2C0_CLKC18TRACE_D7SPIS1_MISOI2C0_SCLHPS_GPIO56
35JTAG Dedicated3.3VJTAG_TDI
36USB DedicatedUSB_VBUS
37JTAG Dedicated3.3VJTAG_TDO
38USB Dedicated3.3VUSB-
39JTAG Dedicated3.3VJTAG_TCK
40USB Dedicated3.3VUSB+
41JTAG Dedicated3.3VJTAG_TMS
42USB Dedicated3.3VUSB_ID
43HPS IO3.3VHPS_GPIO0C21TRACE_CLKHPS_GPIO48
44HPS IO3.3VHPS_GPIO1H13SDMMC_D4USB0_D4HPS_GPIO40
45HPS IO3.3VHPS_GPIO2A4SDMMC_D5USB0_D5HPS_GPIO41
46HPS IO3.3VHPS_GPIO3H12SDMMC_D6USB0_D6HPS_GPIO42
47HPS IO3.3VHPS_GPIO4B4SDMMC_D7USB0_D7HPS_GPIO43
48HPS IO3.3VHPS_GPIO5B12SDMMC_FB_CLK_INUSB0_CLKHPS_GPIO44
49HPS IO3.3VBOOTSEL1A6BOOTSEL1QSPI_SS0HPS_GPIO33
50HPS IO3.3VBOOTSEL2D15BOOTSEL2NAND_WEQSPI_SS1HPS_GPIO28
51PWRGND
52PWRGND
53FPGA IOVariedFPGA_GPIO0AH12
54FPGA IOVariedFPGA_GPIO1AF18
55FPGA IOVariedFPGA_GPIO2AG21
56FPGA IOVariedFPGA_GPIO3AH21
57FPGA IOVariedFPGA_GPIO4AG26
58FPGA IOVariedFPGA_GPIO5AH26
59FPGA IOVariedFPGA_GPIO6AH6
60FPGA IOVariedFPGA_GPIO7AH5
61FPGA IO3.3VFPGA_GPIO8Y11
62FPGA IO3.3VFPGA_GPIO9AA11
63FPGA IO3.3VFPGA_GPIO10AD5
64FPGA IO3.3VFPGA_GPIO11AE6
65FPGA IO3.3VFPGA_GPIO12AF26
66FPGA IO3.3VFPGA_GPIO13AE26
67FPGA IO3.3VFPGA_GPIO14AA20
68FPGA IO3.3VFPGA_GPIO15Y19
69PWRGND
70PWRGND
71FPGA IO3.3VFPGA_GPIO16AE25
72FPGA IO3.3VFPGA_GPIO17AD26
73FPGA IO3.3VFPGA_GPIO18Y17
74FPGA IO3.3VFPGA_GPIO19Y18
75FPGA IO3.3VFPGA_GPIO20AC24
76FPGA IO3.3VFPGA_GPIO21AB23
77FPGA IO3.3VFPGA_GPIO22Y16
78FPGA IO3.3VFPGA_GPIO23AA24
79FPGA POWERFPGA_DDRVREFAF12
80Dedicated3.3VIO_PWR_CTRL0
81FPGA IO3.3VPERST#W15
82Dedicated3.3VIO_PWR_CTRL0
83FPGA IOVariedHS_DIFF_CLKIN0+Y15DIFFIO_RX_B55p
84FPGA IOVariedHS_DIFF_CLKIN1+V12DIFFIO_RX_B39p
85FPGA IOVariedHS_DIFF_CLKIN0-AA15DIFFIO_RX_B55n
86FPGA IOVariedHS_DIFF_CLKIN1-W12DIFFIO_RX_B39n
87PWRGND
88PWRGND
89FPGA IOVariedHS_DIFF_RX0pAF25DIFFIO_RX_B78p
90FPGA IOVariedHS_DIFF_TX0pAF27DIFFIO_TX_B80p
91FPGA IOVariedHS_DIFF_RX0nAG25DIFFIO_RX_B78n
92FPGA IOVariedHS_DIFF_TX0nAF28DIFFIO_TX_B80n
93FPGA IOVariedHS_DIFF_RX1pAC22DIFFIO_RX_B75p
94FPGA IOVariedHS_DIFF_TX1pAG28DIFFIO_TX_B77p
95FPGA IOVariedHS_DIFF_RX1nAC23DIFFIO_RX_B75n
96FPGA IOVariedHS_DIFF_TX1nAH27DIFFIO_TX_B77n
97FPGA IOVariedHS_DIFF_RX2pAE24DIFFIO_RX_B74p
98FPGA IOVariedHS_DIFF_TX2pAG24DIFFIO_TX_B72p
99FPGA IOVariedHS_DIFF_RX2nAE23DIFFIO_RX_B74n
100FPGA IOVariedHS_DIFF_TX2nAH24DIFFIO_TX_B72n
101FPGA IOVariedHS_DIFF_RX3pAG23DIFFIO_RX_B70p
102FPGA IOVariedHS_DIFF_TX3pAH23DIFFIO_TX_B69p
103FPGA IOVariedHS_DIFF_RX3nAF23DIFFIO_RX_B70n
104FPGA IOVariedHS_DIFF_TX3nAH22DIFFIO_TX_B69n
105FPGA IOVariedHS_DIFF_RX4pAD23DIFFIO_RX_B67p
106FPGA IOVariedHS_DIFF_TX4pAF20DIFFIO_TX_B64p
107FPGA IOVariedHS_DIFF_RX4nAE22DIFFIO_RX_B67n
108FPGA IOVariedHS_DIFF_TX4nAG20DIFFIO_TX_B64n
109PWRGND
110PWRGND
111FPGA IOVariedHS_DIFF_RX5pAF22DIFFIO_RX_B66p
112FPGA IOVariedHS_DIFF_TX5pAG19DIFFIO_TX_B61p
113FPGA IOVariedHS_DIFF_RX5nAF21DIFFIO_RX_B66n
114FPGA IOVariedHS_DIFF_TX5nAH19DIFFIO_TX_B61n
115FPGA IOVariedHS_DIFF_RX6pAE20DIFFIO_RX_B62p
116FPGA IOVariedHS_DIFF_TX6pAG18DIFFIO_TX_B60p
117FPGA IOVariedHS_DIFF_RX6nAD20DIFFIO_RX_B62n
118FPGA IOVariedHS_DIFF_TX6nAH18DIFFIO_TX_B60n
119FPGA IOVariedHS_DIFF_RX7pAA19DIFFIO_RX_B59p
120FPGA IOVariedHS_DIFF_TX7pAH17DIFFIO_TX_B56p
121FPGA IOVariedHS_DIFF_RX7nAA18DIFFIO_RX_B59n
122FPGA IOVariedHS_DIFF_TX7nAH16DIFFIO_TX_B56n
123FPGA IOVariedHS_DIFF_RX8pAE19DIFFIO_RX_B58p
124FPGA IOVariedHS_DIFF_TX8pAG15DIFFIO_TX_B53p
125FPGA IOVariedHS_DIFF_RX8nAD19DIFFIO_RX_B58n
126FPGA IOVariedHS_DIFF_TX8nAH14DIFFIO_TX_B53n
127PWRGND
128PWRGND
129FPGA IOVariedHS_DIFF_RX9pAD17DIFFIO_RX_B54p
130FPGA IOVariedHS_DIFF_TX9pAG14DIFFIO_TX_B52p
131FPGA IOVariedHS_DIFF_RX9nAE17DIFFIO_RX_B54n
132FPGA IOVariedHS_DIFF_TX9nAH13DIFFIO_TX_B52n
133FPGA IOVariedHS_DIFF_RX10pW14DIFFIO_RX_B51p
134FPGA IOVariedHS_DIFF_TX10pAG11DIFFIO_TX_B48p
135FPGA IOVariedHS_DIFF_RX10nV13DIFFIO_RX_B51n
136FPGA IOVariedHS_DIFF_TX10nAH11DIFFIO_TX_B48n
137FPGA IOVariedHS_DIFF_RX11pAF17DIFFIO_RX_B50p
138FPGA IOVariedHS_DIFF_TX11pAG10DIFFIO_TX_B45p
139FPGA IOVariedHS_DIFF_RX11nAG16DIFFIO_RX_B50n
140FPGA IOVariedHS_DIFF_TX11nAH9DIFFIO_TX_B45n
141FPGA IOVariedHS_DIFF_RX12pAF15DIFFIO_RX_B46p
142FPGA IOVariedHS_DIFF_TX12pAG9DIFFIO_TX_B44p
143FPGA IOVariedHS_DIFF_RX12nAE15DIFFIO_RX_B46n
144FPGA IOVariedHS_DIFF_TX12nAH8DIFFIO_TX_B44n
145PWRGND
146PWRGND
147FPGA IOVariedHS_DIFF_RX13pU14DIFFIO_RX_B43p
148FPGA IOVariedHS_DIFF_TX13pAG8DIFFIO_TX_B41p
149FPGA IOVariedHS_DIFF_RX13nU13DIFFIO_RX_B43n
150FPGA IOVariedHS_DIFF_TX13nAH7DIFFIO_TX_B41n
151FPGA IOVariedHS_DIFF_RX14pAE12DIFFIO_RX_B38p
152FPGA IOVariedHS_DIFF_TX14pAG5DIFFIO_TX_B37p
153FPGA IOVariedHS_DIFF_RX14nAD12DIFFIO_RX_B38n
154FPGA IOVariedHS_DIFF_TX14nAH4DIFFIO_TX_B37n
155FPGA IOVariedHS_DIFF_RX15pAD11DIFFIO_RX_B30p
156FPGA IOVariedHS_DIFF_TX15pAF7DIFFIO_TX_B33p
157FPGA IOVariedHS_DIFF_RX15nAE11DIFFIO_RX_B30n
158FPGA IOVariedHS_DIFF_TX15nAG6DIFFIO_TX_B33n
159FPGA IOVariedHS_DIFF_RX16pAF11DIFFIO_RX_B34p
160FPGA IOVariedHS_DIFF_TX16pAH3DIFFIO_TX_B36p
161FPGA IOVariedHS_DIFF_RX16nAF10DIFFIO_RX_B34n
162FPGA IOVariedHS_DIFF_TX16nAH2DIFFIO_TX_B36n
163PWRGND
164PWRGND
165FPGA IOVariedHS_DIFF_RX17pAD10DIFFIO_RX_B26p
166FPGA IOVariedHS_DIFF_TX17pAE8DIFFIO_TX_B29p
167FPGA IOVariedHS_DIFF_RX17nAE9DIFFIO_RX_B26n
168FPGA IOVariedHS_DIFF_TX17nAF9DIFFIO_TX_B29n
169FPGA IOVariedHS_DIFF_RX18pT11DIFFIO_RX_B27p
170FPGA IOVariedHS_DIFF_TX18pAE4DIFFIO_TX_B25p
171FPGA IOVariedHS_DIFF_RX18nU11DIFFIO_RX_B27n
172FPGA IOVariedHS_DIFF_TX18nAF4DIFFIO_TX_B25n
173FPGA IOVariedHS_DIFF_RX19pT13DIFFIO_RX_B35p
174FPGA IOVariedHS_DIFF_TX19pAE7DIFFIO_TX_B28p
175FPGA IOVariedHS_DIFF_RX19nT12DIFFIO_RX_B35n
176FPGA IOVariedHS_DIFF_TX19nAF8DIFFIO_TX_B28n
177FPGA IOVariedHS_DIFF_RX20pAG13DIFFIO_RX_B42p
178FPGA IOVariedHS_DIFF_TX20pAF5DIFFIO_TX_B32p
179FPGA IOVariedHS_DIFF_RX20nAF13DIFFIO_RX_B42n
180FPGA IOVariedHS_DIFF_TX20nAF6DIFFIO_TX_B32n
181PWRGND
182PWRGND
183HPS Dedicated3.3VHPS_RESET#H19
184Transceiver Dedicated1.5VGXB_REF_CLKpV5
185HPS Dedicated3.3VHPS_WARM_RST#A23
186Transceiver Dedicated1.5VGXB_REF_CLKnV4
187PWRGND
188PWRGND
189Transceiver Dedicated1.5VGXB_RX_p0AF2
190Transceiver Dedicated1.5VGXB_TX_p0AD2
191Transceiver Dedicated1.5VGXB_RX_n0AF1
192Transceiver Dedicated1.5VGXB_TX_n0AD1
193PWRGND
194PWRGND
195Transceiver Dedicated1.5VGXB_RX_p1AB2
196Transceiver Dedicated1.5VGXB_TX_p1Y2
197Transceiver Dedicated1.5VGXB_RX_n1AB1
198Transceiver Dedicated1.5VGXB_TX_n1Y1
199PWRGND
200PWRGND
201Transceiver Dedicated1.5VGXB_RX_p2V2
202Transceiver Dedicated1.5VGXB_TX_p2T2
203Transceiver Dedicated1.5VGXB_RX_n2V1
204Transceiver Dedicated1.5VGXB_TX_n2T1
205PWRGND
206PWRGND
207Transceiver Dedicated1.5VGXB_RX_p3P2
208Transceiver Dedicated1.5VGXB_TX_p3M2
209Transceiver Dedicated1.5VGXB_RX_n3P1
210Transceiver Dedicated1.5VGXB_TX_n3M1
211PWRGND
212PWRGND
213Transceiver Dedicated1.5VGXB_RX_p4K2
214Transceiver Dedicated1.5VGXB_TX_p4H2
215Transceiver Dedicated1.5VGXB_RX_n4K1
216Transceiver Dedicated1.5VGXB_TX_n4H1
217PWRGND
218PWRGND
219Transceiver Dedicated1.5VGXB_RX_p5F2
220Transceiver Dedicated1.5VGXB_TX_p5D2
221Transceiver Dedicated1.5VGXB_RX_n5F1
222Transceiver Dedicated1.5VGXB_TX_n5D1
223PWR InputVCC_+5V
224PWR InputVCC_+5V
225PWR InputVCC_+5V
226PWR InputVCC_+5V
227PWR InputVCC_+5V
228PWR InputVCC_+5V
229PWR InputVCC_+5V
230PWR InputVCC_+5V

Notes:
1) For more information about pin definitions and pin connection guidelines please refer to the Cyclone V Device Family Pin Connection Guidelines (http://www.altera.com/literature/dp/cyclone-v/PCG-01014.pdf)

 

Module Reset

Both reset connections are available on the edge connector. The Cold reset is asserted active-low at power-on until all the monitored power supply rails are alive. The Warm reset is also available as a less severe reset signal. Consult the Altera documentation for the differences between the two reset signals. Note that both resets are active-low and can be read or driven by the Cubic-SoC. These should be driven by an open-collector output and pull-up resistors are included on the module, so they are not necessary on the carrier board.

JTAG / TRACE

The JTAG and TRACE interface signals for the processor have been brought out through card edge connector. The JTAG connections are routed to a debug header on the carrier board. The TRACE interface, which can be routed to the debug header on the carrier board, requires additional ARM debug hardware to take advantage of.

Module Boot Configuration

Boot options are defined by three sets of inputs: MSEL, BSEL, and CSEL. MSEL defines the FPGA configuration scheme. BSEL identifies the boot device to try first for the HPS. Note that the HPS will try additional boot sources if the boot selection initially fails. CSEL is the clock selection and defined the clock divisors to use after reset.

Defining the desired FPGA configuration mode is done through the MSEL input pins. These are dedicated inputs that be connected to power or ground with low impedance paths on the SOM. The default MSEL code is 00010. Additionally, they need to be valid at power-on and the high state cannot be gated by the I/O power enable.

The BSEL inputs are multi-function pins. At reset, they are read to determine the desired boot device. After reset, they are used for other I/O functions. These are pulled high or low through 10Kohm resistors on the SOM. If you want to change default BSEL code, lower resistors should be used as pull-up or pull-down on the carried board. The BSEL nets are in the power domains of their respective Banks in the FPGA.

Lastly, the CSEL inputs define the clock scheme coming out of reset. These are also multi-function pins, read during reset and other Bank7A I/O pins after reset. Being in Bank7A, their power domain is +3.3V. These are pulled high or low through 10Kohm resistors on the SOM. Add a pull-up or pull-down resistor on the carried board to define the desired clock option.

 

Electrical Requirements

Power Supplies

The module takes 5V power in and generates all the supply rails required for the FPGA core and HPS peripherals. The 5V power can be supplied by card edge pins. USB connector power supply can be used when power consumption less than 2.5W.

Mechanical Requirements

Module Connectors

The Cubic-SoC-5CSX module mates with a single connector that contains all of the power and I/O for the module. The mating socket is a 230-pin MXM 2.0 type connector which is also used for PCI Express capable notebook graphics cards following the MXM specification. Therefore, this connector type is also known as a MXM connector.

The MXM edge connector is the result of an extensive collaborative design effort with the industry’s leading notebook manufacturers. This collaboration has produced a robust, low-cost edge connector that is capable of handling high-speed serialized signals. The MXM connector accommodates various connector heights for different carrier board applications needs. This specification suggests two connector heights, 7.8mm and 5.5mm.

Table 6 MXM2.0 Connector

ManufacturerPart NumberResulting height
between module and baseboard
Overall height of the connector
FoxconnAS0B326-S78N-7F5.0mm7.8mm
FoxconnAS0B326-S55N-7F2.7mm5.5mm
SpeedtechB33P102-XX1X5.0mm7.5mm
SpeedtechB33P102-XX2X2.7mm5.2mm

 

Mounting Methods

The MXM connector has no latch arms for retaining the module. Instead, there are two corner mounting holes for securing the module. This provides a secure means of fastening the module in an embedded design for reliable performance.

Schematic Guidelines

Reset

Power-On Reset (POR)

The power-on reset is an input-only signal with a pull-up resistor to +3.3V on the module. This input can be driven low to force a cold reset, placing the SoC in a mode equivalent to the power-on state. This should be driven with an open connector signal if actively driven.

PWarm Reset (RST)

The warm reset is a bidirectional signal. A reset monitor is recommended, but not required. When choosing the reset monitor, choose one with an open collector output to avoid contention on the line. This input can be driven low, but avoid driving it high – the pull-up on the module will provide the high level once the power supplies have all started up.

Power Input

Although an option of power supply is using usb connector +5V input, in order to get more power, we recommended the +5V power source is supplied from carrier board by card edge connector.

VIO Support

Up to 112 FPGA I/O pins are available externally to a module, including 84 pins which voltage can be adjustable. The I/O standards of the FPGA pins can be adjusted via two system control signal named VCCIO_S0 and VCCIO_S1, which are located on card edge connector pin 80 and pin 82. Table 3 lists the settings for selecting FPGA I/O voltage standard.

Adjustable standards allow even more flexibility and selection of daughter cards or interconnect devices. For example, the voltage standard is adjusted 1.5V used for DDR3 memory interface, and is adjusted 2.5V used for dedicated serializer/deserializer (SERDES). Users must ensure that the voltage standards for both the module and carrier board are the same, or damage and incompatibility may occur.

The VREF connections are tied to voltage dividers that supply a reference voltage set to half the VIO voltage for each bank. The VREF of BANK3A and BANK4B are tied together , which is bought out by card edge pin 79. If external memory on FPGA is needed , this pin should tie the reference voltage of memory. Connect to ground directly when it is not used.

 

GbE Ethernet and USB – Special Considerations

Due to critical timing that exists between the physical PHYs for the Gigabit Ethernet and USB2.0 interfaces to the associated HPS controllers in the Cyclone V devices, Cubic-SoC SOM is designed to implement the Gigabit Ethernet and USB 2.0 PHYs. The outputs of the PHYs are the connected to card edge connector. It is the responsibility of the carrier borad designer to implement the proper connections to an RJ45 connector for Gigabit Ethernet and a USB connector for its USB2.0 interface.

PCIe Hard IP

The PCIe Hard IP can be configured to run a x1, x2, or x4 PCIe interface. It will generally be a root port, but can also be configured as a peripheral endpoint device. When used as an endpoint, the configuration via protocol (CvP) is supported by the production silicon modules.

If planning to use the Hard PCI Express controller, use the low transceivers and reference clock. The PCI Express reset signal , named PERST#, is on Bank5A and is available on the edge connector pin 81. This signal will be on the 3.3V voltage provided by the carrier board. Configure this pin as an open collector and drive it low when active or let it float high with the external pull–up resistor. The voltage on this I/O is safe with a 10K pull-up resistor.

 

Assigning I/O Pins

Besides the HPS peripherals, there are multiple banks available for the I/O pin assignments. To identify the best pin assignment option, try to follow the guidelines below. The simplest path is if all the I/Os use the same VIO voltage, so that is addressed first.

FPGA Fabric I/O Pins

An example of this case would be a mix of +2.5V LVCMOS or LVTTL signals along with LVDS differential pairs.

Start with the highest bandwidth signals. Identify the clocking scheme that will be used for these high bandwidth interfaces. Note that the clocks are distributed efficiently in quadrants within the FPGA. If the clock needs to cross the quadrant boundary, it goes through a clock crossing and there will be additional jitter and more difficulty in meeting timing in the FPGA design. The best performance is achieved when the clock is brought in on a dedicated clock input pin or pair of pins. It is highly recommended that the data pins associated with that clock are in the same quadrant. When assigning clock pins, note that there is only one dedicated clock route to the fractional PLL for each clock input pair. If using a single-ended clock input, choose the positive input pin of the clock pair because this has the connection to the dedicated clock route. The negative input of the pair will use an more general clock routing resource to reach the fPLL and incur additional jitter.

If additional clock inputs are required, they can be used directly on other input pins, but cannot be routed to fPLLs. Non-dedicated input pins and logic can drive regional clock resources.

Once the clock is identified, assign the data pins. For any inputs that need the extra bandwidth available by using the SERDES blocks, make sure they are assigned to pin locations that include the proper dedicated SERDES signaling direction. Once the first interface is allocated, build up a simple FPGA project and verify the pin allocation and timing constraints can be met.

Use the Quartus TimeQuest Timing Analyzer Wizard to generate the clock constraints for the design. Use the Quartus Pin Planner to assign the pins allocated in the design. For the data lanes, connect up some simple logic that instantiates the SERDES blocks as necessary for the design and consumes the data or generates data for an active design. Once the prototype logic is ready, compile the design and make sure the pin assignments are valid and the logic did not get stripped out due to constant values or lack of a data consumer.

Once the first interface is prototyped and pin assignments are validated, move on to the next interface. Work through each group of signals and adjust the assignments as necessary to meet the rules and timing requirements for the design.

 

Accessing More of the HPS Peripherals

The HPS pin MUX options have limited means of connecting directly to the hard MAC blocks in the HPS. For example, a typical design will use one RGMII Ethernet interface and the module’s included USB interface. With these two interfaces assigned, there is no place to bring out the second of either directly on the HPS pins.

These additional peripherals can still be utilized and the design can take advantage of the Hard MAC blocks. The FPGA design can pass the additional peripheral connections to the FPGA fabric and use the FPGA I/O pins to connect to the PHY.

 

Additional FPGA I/O Pins

A similar need may be a design that requires additional FPGA I/O connections instead of the HPS Peripherals. The HPS pins that are connected to the edge connector can be passed to the FPGA fabric instead of controlled by the HPS peripherals. To use this feature, the Loan-IO settings would be used in the HPS settings under QSYS. Note that these pins may be more difficult to work with for higher speed interfaces. It is recommended to build the FPGA design in Quartus to validate the timing constraints before committing to the PCB.

 

Board Layout Guidelines

Power Supply and Decoupling Capacitors

Switching supplies are recommended as the best design practice. These reduce wasted power and result in a better product design. As temperature increases in a design, the cooling requirements become more onerous. Higher temperatures also increase part failures and reduce the MTBF of a design. When designing the layout of a switcher power supply, pay particular attention to the high current switching loops through the supply, inductor, and caps at the output. The input has similar current loops to supply the power and there needs to be small, fast response, caps close to the power supply input pins and the larger bulk capacitor can be placed a little farther away. Keeping these current loops small will result in a more stable design that also minimizes EMI challenges.

Ensure the power supplies have sufficient capacitance. The design must include a good mix of high frequency ceramic caps close to the power pins as well as the slower large bulk caps to maintain the rails. For best results, place vias to the side of capacitor footprints instead of at the end. Also, keep the power and ground connection vias close to the capacitor footprint.

Critical Routing

Differential pairs and single ended signals are available for custom carrier card designs. As interface speeds increase, the board layout becomes increasingly important. All high speed routing must follow the specific device manufacturers’ recommendations for routing, impedance, trace length and layout guidelines. This is applicable to any high speed or low noise signals such as DDR RAM, Ethernet PHY or USB extensions. The design engineer must be diligent in these areas to ensure intended data rates and performance. To have a successful design, ensure there is a solid reference plane under all high speed signals. These include any signals running at speeds of 100MHz or higher when short traces can be used. This requirement extends to slower signals as the trace length increases. For best results, keep the wide bus interface and high speed signals short.

 

Global Target Impedances (Unless otherwise noted)

 100Ω differential impedance
 50Ω single ended impedance
 USB: 45Ω single ended, 90Ω differential

 

Pair Matching and Length Tuning

 Use 4x spacing between pairs
 All signals should be routed using strip line or micro strip techniques
 Length tune all signal pairs to within 10 mils within each pair (P to N)
 Length tune all signal pairs to within 250 mils pair-to-pair (depending on transfer rates)

 

LVDS Interfaces for High Bandwidth

The Cyclone V include SERDES blocks for high speed serialization and deserialization. These hard IP blocks are included in most of the fabric I/Os. Note however, that each pair can only operate at the highest data rates in one direction. All the LVDS pairs can be input or output, but there is additional bandwidth available if the SERDES block is utilized in the design.

To ease design of boards that require the highest bandwidth, the LVDS pairs have been noted on the edge connector to include the higher performance SERDES direction. In general, the SERDES TX pairs are on the top edge connector pins and the SERDES RX pairs are on the bottom edge connector. All this signals locate Bank3B and Bank4A.

The Cyclone V FPGA has some pin allocation requirements that define how a mix of single ended I/O pins and differential pairs can be placed. Before releasing a board design for fabrication, prototype the FPGA design enough to validate the pin assignments. Verify all the pin assignments are defined in a Quartus project and make sure a successful build can be generated.

 

Thermal Management

The thermal management of the full system should be considered carefully to create a reliable end product. With the Cubic-SoC module in a system, the FPGA is likely a large part of the control unit for a product. It has a wide range of power consumption that is defined by a number of factors specific to each application.

Users need to review the power consumption for their target application and address the thermal management as well. Some references are available to help identify the amount of power and heat generated by the FPGA. On the module, the power supplies and interfaces were designed with efficiency in mind.

 

Module Thermal Information

The information in Table 27 is provided to give an idea of maximum power consumption for a demanding application. For best results, the Early Power Estimator should be used with details for the specific application. The numbers in Table 27 include all the interfaces on the module as well as an RGMII interface to represent a reasonable maximum, but the Phy would reside on the carrier board. The Bank3B and Bank4A I/O interfaces are dependent on the carrier board design and are not included in the calculations. This is limited to I/O power for those banks and that power will minimally contribute to the heat load of the module. The one exception that should be noted is the power consumed in the on chip termination if used in a design.

The EPE spreadsheet provides various application benchmarks for checking HPS power consumption. The information should be filled out and calculated for the specific application needs as there is a wide range of power the device could consume. For some ways to save power, it is possible to run the HPS and logic at lower clock rates to save power.

 

Thermal Performance

Most designs will need some form of additional heat sink or active cooling to maintain the junction temperature within device limits. A fully loaded design will require significant cooling to operate reliably across the full commercial or industrial temperature range.

Designs that are not pushing the capabilities of the Cyclone V and HPS performance can use various strategies to limit the power consumed. Some typical strategies to pursue are running the HPS core clock frequency at a reduced rate. The Cubic-SoC modules default to the 800MHz HPS operating frequency. Setting this to a slower clock rate will reduce the dynamic power consumption. The static power consumption is based on the leakage of the internal features and cannot be reduced easily.

When designing the FPGA logic, design choices play an important role in determining the power consumed. Faster clocks will consume more power proportional to the clock rate. Isolating the fast logic sections of a design and running logic slower where possible will provide a few benefits. Some of the benefits include reduced power consumption, and quicker compiles. At fast clock rates, the QuartusII tools will have to work harder to meet timing. If the tools have difficulty in meeting timing, this will generally require longer design compiles.

Fast I/O pins will also consume more power. If fast interfaces are desired, reduce the voltage standard where possible. Also reduce the capacitive load on the I/O connections in PCB layout. The dynamic power requirements increase linearly with the capacitance an I/O has to charge and discharge at each transition. The voltage is more significant because this term is exponential. Checking various design scenarios is easily performed with the Early Power Estimator7 and entering the I/O characteristics into the fields on the spreadsheet for each group of signals to get an estimate. As a design progresses, QuartusII design details can be loaded into the EPE to get better estimates of power requirements.

 

NOTE

Altera has identified an errata with the HPS PLL where it will sometimes fail to lock at reset. When this happens the HPS may hang during the BootROM stage and fail to proceed to the Preloader, or it may fail SDRAM calibration during the Preloader. To avoid this errata, follow the workaround provided by Altera. This includes setting the CSEL to 00 to bypass the PLL at reset and apply the patch to the Preloader.